TOE1G-IP core for FPGA
You can implement TCP/IP communication functionality with pure hardware logic without a CPU!
The TCP Offloading Engine IP Core (TOE1G-IP) is a groundbreaking solution that enables the complex TCP transmission and reception processes, which traditionally required expensive high-end CPUs, to be implemented solely with pure hardware logic without a CPU. It comes standard with a reference design compatible with Xilinx/Altera FPGAs, which can help shorten product development time.
- Company：デザイン・ゲートウェイ
- Price：Other
